Computing, communications, consumer electronics and other processor-based systems are driven to host a larger number of applications, each with increasing complexity. The transfer of information and signals required among the components of these processor-based systems leads to increasing demands on the devices involved in transfer of data.
For example, as memory system speeds and capacity increase to satisfy the demand for more applications, maintaining good signal integrity becomes increasingly difficult. In memory systems that support multi-drop data topologies, which allow more than one device per data signal and support upgradeability by allowing multiple modules to be plugged into the bus, increases in capacity can degrade signal integrity, and as a result, decrease the maximum speed of operation of the memory system. In general, point-to-point signaling topologies (one device at each end of the signal line) have good signal integrity properties and even higher bus speeds but implementing upgradeability so as to support the addition of different of memory module can be complex depending on the types of memory involved.
One exemplary memory type that can be used with these systems is a double-data rate synchronous dynamic random access memory (e.g., the DDR-SDRAM family of products, which includes products of all DDR generations, including DDR1, DDR2, DDR3, DDR4, etc.). The DRAM is considered synchronous as it coordinates its operations to a provided clock signal, and it is considered double-data rate as it transfers data on both the rising and falling edge of the clock. DDR DRAM devices transmit and receive data using a strobe-based method. In this method, a strobe signal (referred to as the DQS signal in DDR-SDRAM parlance) is edge-aligned to and accompanies a group of data signals (referred to as the DQ signals in DDR-SDRAM parlance) sent by the DRAM in a “read” operation, and is center-aligned (also referred to as “quadrature aligned”, as DQS is offset from the data edge by a quarter of the clock cycle time) to and accompanies the DQ signals in a “write” operation. This DQS signal is used by the receiving device to time the sampling of the data signal. In the memory controller (which is the receiving device during memory read operations), the DQS signal and the data are received and the DQS signal is then delayed by some fixed amount, nominally one-fourth of the memory system clock period. This delayed DQS signal, which is now approximately in quadrature with the received data, is then used as a common sample clock for each of the DQ input receivers for a particular number of bits of data associated with the strobe signal.
It may be desirable to implement such devices with different types of memory buses while maintaining general principles of operation for the system.